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19-2431; Rev 0; 7/02
KIT ATION EVALU ILABLE AVA
Dual 180 Out-of-Phase PWM StepDown Controllers with POR
General Description Features
o Two Independent Output Voltages o 180 Out-of-Phase Operation o 90 Out-of-Phase Operation (Using Two MAX1875/MAX1876s) o Foldback Current Limit o 4.75V to 23V Input Supply Range o 0 to 18V Output-Voltage Range (Up to 10A) o >90% Efficiency o Fixed-Frequency Pulse-Width Modulation (PWM) Operation o Adjustable 100kHz to 600kHz Switching Frequency o External SYNC Input o Clock Output for Master/Slave Synchronization o Soft-Start and Soft-Stop o RST Output with 140ms Minimum Delay (MAX1876) o Lossless Current Limit (No Sense Resistor)
MAX1875/MAX1876
The MAX1875/MAX1876 dual, synchronized, step-down controller generates two outputs from input supplies ranging from 4.75V to 23V. Each output is adjustable from sub-1V to 18V and supports loads of 10A or higher. Input voltage ripple and total RMS input ripple current are reduced by synchronized 180 out-of-phase operation. The switching frequency is adjustable from 100kHz to 600kHz with an external resistor. Alternatively, the controller can be synchronized to an external clock generated to another MAX1875/MAX1876 or a system clock. One MAX1875/MAX1876 can be set to generate an inphase, or 90 out-of-phase, clock signal for synchronization with additional controllers. This allows two controllers to operate either as an interleaved two- or four-phase system with each output shifted by 90. These devices also feature soft-start and soft-stop. The MAX1875/MAX1876 eliminate the need for currentsense resistors by utilizing the low-side MOSFET's onresistance as a current-sense element. This protects the DC-DC components from damage during outputoverload conditions or when output short-circuit faults without requiring a current-sense resistor. Adjustable foldback current limit reduces power dissipation during short-circuit conditions. The MAX1876 includes a power-on reset output to signal the system when both outputs reach regulation. The MAX1875/MAX1876 are available in a 24-pin QSOP package. An evaluation kit is available to speed designs.
Ordering Information
PART MAX1875EEG MAX1876EEG TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 24 QSOP 24 QSOP
Applications
Network Power Supplies Telecom Power Supplies DSP, ASIC, and FPGA Power Supplies Set-Top Boxes Broadband Routers Servers
Pin Configuration
TOP VIEW
COMP2 1 FB2 2 ILIM2 3 OSC 4 V+ 5 REF 6 GND 7 24 EN 23 DH2 22 LX2 21 BST2 20 DL2
MAX1875/ MAX1876
19 VL 18 PGND 17 DL1 16 BST1 15 LX1 14 DH1 13 RST (MAX1876 ONLY)
Typical Operating Circuit appears at end of data sheet.
CKO 8 SYNC 9 ILIM1 10 FB1 11 COMP1 12
QSOP
________________________________________________________________ Maxim Integrated Products
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +25V PGND to GND .......................................................-0.3V to +0.3V VL to GND ..................-0.3V to the lower of +6V and (V+ + 0.3V) BST1, BST2 to GND ...............................................-0.3V to +30V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) DL1, DL2 to PGND........................................-0.3V to (VL + 0.3V) CKO, REF, OSC, ILIM1, ILIM2, COMP1, COMP2 to GND ..........................-0.3V to (VL + 0.3V) FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6V VL to GND Short Circuit .............................................Continuous REF to GND Short Circuit ...........................................Continuous Continuous Power Dissipation (TA = +70C) 24-Pin QSOP (derate 9.4mW/C above +70C)...........762mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22F, CVL = 4.7F (ceramic), ROSC = 60k, compensation components for COMP_ are from Figure 1, TA = -40C to +85C (Note 1), unless otherwise noted.)
PARAMETER GENERAL V+ Operating Range V+ Operating Supply Current V+ Standby Supply Current Thermal Shutdown Current-Limit Threshold VL REGULATOR Output Voltage VL Undervoltage Lockout Trip Level REFERENCE Output Voltage Reference Load Regulation SOFT-START Digital Ramp Period Soft-Start Steps FREQUENCY Low End of Range High End of Range DH_ Minimum Off-Time ROSC = 60k ROSC = 10k ROSC = 10k 0C to +85C -40C to +85C 84 80 540 100 100 600 250 115 120 660 303 kHz kHz ns Internal 6-bit DAC for one converter to ramp from 0V to full scale (Note 3) 1024 64 DC-DC Clocks Steps IREF = 0A 0A < IREF < 50A 1.98 0 2.00 4 2.02 10 V mV (Note 2) VL = V+ (Note 2) VL unloaded, no MOSFETs connected EN = LX_ = FB_ = 0V ROSC = 60k ILIM_ = VL PGND - LX_ RILIM_ = 100k RILIM_ = 600k 5.5V < V+ < 23V, 1mA < ILOAD < 50mA 75 32 225 4.75 4.4 Rising temperature, typical hysteresis = 10C 4.75 4.75 3.5 0.3 160 100 50 300 5 4.55 125 62 375 5.25 4.7 23 5.5 6 0.6 V mA mA C mV mV mV V V CONDITIONS MIN TYP MAX UNITS
2
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22F, CVL = 4.7F (ceramic), ROSC = 60k, compensation components for COMP_ are from Figure 1, TA = -40C to +85C (Note 1), unless otherwise noted.)
PARAMETER SYNC Range SYNC Input Pulse Width SYNC Rise/Fall Time ERROR AMPLIFIER FB_ Input Bias Current FB_ Input Voltage Set Point FB_ to COMP_ Transconductance DRIVERS DL_, DH_ Break-Before-Make Time CLOAD = 5nF Low DH_ On-Resistance High DL_ On-Resistance LOGIC INPUTS (EN, SYNC) Input Low Level Input High Level Input High/Low Bias Current LOGIC OUTPUTS (CKO) Output Low Level Output High Level COMP_ Pulldown Resistance During Shutdown and Current Limit RST OUTPUT (MAX1876 ONLY) Output-Voltage Trip Level Output Low Level Output Leakage Reset Timeout Period FB_ to Reset Delay Both FBs must be over this to allow the reset timer to start; there is no hysteresis VL = 5V, sinking 3.2mA VL = 1V, sinking 0.4mA V+ = VL = 5V, V RST = 5.5V, VFB = 1V VFB_ = 1V FB_ overdrive from 1V to 0.85V 140 315 4 0.87 0.9 0.93 0.4 0.3 1 560 V V A ms s 17 VL = 5V, sinking 5mA VL = 5V, sourcing 5mA 4.0 0.4 V V Typical 15% hysteresis, VL = 4.75V VL = 5.5V VEN = 0 or 5.5V 2.4 -1 0.1 +1 0.8 V V A Low High 30 1.5 3 0.6 3 2.5 5 1.5 5 ns 0C to +85C -40C to +85C 0C to +85C -40C to +85C 0.985 0.98 1.25 1.2 1.00 1.00 1.8 1.8 250 1.015 1.02 2.70 2.9 nA V mS CONDITIONS Internal oscillator nominal frequency must be set to half of the SYNC frequency (Note 3) (Note 3) High Low MIN 200 100 100 100 TYP MAX 1200 UNITS kHz ns ns
MAX1875/MAX1876
Note 1: Specifications to -40C are guaranteed by design and not production tested. Note 2: Operating supply range is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation. Note 3: Guaranteed by design and not production tested.
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD
MAX1875 toc01
OUTPUT-VOLTAGE ACCURACY vs. LOAD
0.8 OUTPUT VOLTAGE ACCURACY (%) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 OUT2 OUT1
MAX1875 toc02
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 LOAD (A) 10 OUT2 OUT1
1.0
100
0
5 LOAD (A)
10
15
VL VOLTAGE ACCURACY vs. LOAD CURRENT
MAX1875 toc03
SWITCHING FREQUENCY vs. ROSC
MAX1875 toc04
0.5
600 500 400 300 200 100 0
0 VL VOLTAGE ACCURACY
-0.5
-1.0
-1.5
-2.0 0 50 100 150 LOAD CURRENT (mA)
SWITCHING FREQUENCY (kHz)
0
10
20
30 ROSC (k)
40
50
60
LOAD TRANSIENT RESPONSE (OUTPUT 1)
MAX1875 toc05
LOAD TRANSIENT RESPONSE (OUTPUT 2)
MAX1875 toc06
VOUT2 50mV/div AC-COUPLED VOUT1 50mV/div AC-COUPLED 10A IOUT1 0A 10s/div 10s/div
VOUT1 50mV/div AC-COUPLED VOUT2 50mV/div AC-COUPLED 10A IOUT2 0A
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, TA = +25C, unless otherwise noted.)
SOFT-START AND SOFT-STOP WAVEFORM
MAX1875 toc07
RESET TIMEOUT (MAX1876 ONLY)
MAX1875 toc08
OUT-OF-PHASE WAVEFORM
MAX1875 toc09
5V/div 5V EN 0V EN 0 VOUT2 VOUT2 1V/div 0V VOUT2 1V/div 0V 0V VOUT1 0V VRST 0V
VOUT1 20mV/div 12V VLX1 0V 12V VLX2 0V VOUT2 20mV/div 1s/div
1ms/div
100ms/div
EXTERNALLY SYNCHRONIZED SWITCHING WAVEFORM
MAX1875 toc10
CKO OUTPUT WAVEFORM
5V VSYNC 0V 5V VCK0 0V 10V VLX1 0V VOUT1 10mV/div AC-COUPLED
MAX1875 toc11
CKO OUTPUT WAVEFORM
MAX1875 toc12
SYNC = GND 5V VCK0 0V 10V VLX1 0V VOUT1 10mV/div AC-COUPLED 400ns/div
SYNC = VL 5V VCK0 0V 10V VLX1 0V VOUT1 10mV/div
400ns/div
400ns/div
SHORT-CIRCUIT CURRENT FOLDBACK AND RECOVERY
MAX1875 toc13
IOUT1 = 10A(5A/div) VOUT1 = 1.8V(1V/div)
SHORT VOUT2
VOUT2 = 2.5V(1V/div) IOUT2 = 10A(5A/div)
4ms/div
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
Pin Description
PIN NAME FUNCTION Compensation Pin for Regulator 2 (REG2). Compensate REG2's control loop by connecting a series resistor (RCOMP2) and capacitor (CCOMP2A) to GND in parallel with a second compensation capacitor (CCOMP2B) as shown in Figure 1. Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive-divider between REG2's output and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB2 to a resistive voltage-divider from REF to REG2's output. See the Setting the Output Voltage section. Current-Limit Adjustment for Regulator 2 (REG2). The PGND-LX2 current-limit threshold defaults to 100mV if ILIM2 is connected to VL. Connect a resistor (RILIM2) from ILIM2 to GND to adjust the REG2's current-limit threshold (VITH2) from 50mV (RILIM2 = 100k) to 300mV (RILIM2 = 600k). See the Setting the Valley Current Limit section. Oscillator Frequency Set Input. The controller generates the clock signal by dividing down the oscillator, so the switching frequency equals half the synchronization frequency (fSW = fOSC/2). Connect a resistor from OSC to GND (ROSC) to set the switching frequency from 100kHz (ROSC = 60k) to 600kHz (ROSC = 10k). The controller still requires ROSC when an external clock is connected to SYNC. When using SYNC, set ROSC for one half of the SYNC input. Input Supply Voltage. 4.75V to 23V. 2V Reference Output. Bypass to GND with a 0.22F or greater ceramic capacitor. Analog Ground Clock Output. Clock Output for external 2- or 4-phase synchronization (see the Clock Synchronization (SYNC, CKO) section). Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect SYNC to a 200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase operation as a master controller. Connect SYNC to VL for 4-phase operation as a master controller (see the Clock Synchronization (SYNC, CKO) section). Current-Limit Adjustment for Regulator 1 (REG1). The PGND-LX1 current-limit threshold defaults to 100mV if ILIM1 is connected to VL. Connect a resistor (RILIM1) from ILIM1 to GND to adjust REG1's current-limit threshold (VITH1) from 50mV (RILIM1 = 100k) to 300mV (RILIM1 = 600k). See the Setting the Valley Current Limit section. Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive-divider between REG1's output and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB1 to a resistive voltage-divider from REF and REG1's output. See the Setting the Output Voltage section. Compensation Pin for Regulator 1 (REG1). Compensate REG1's control loop by connecting a series resistor (RCOMP1) and capacitor (CCOMP1A) to GND in parallel with a second compensation capacitor (CCOMP1B) as shown in Figure 1. Open-Drain Reset Output (MAX1876 only). RST is low when either output voltage is more than 10% below its regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output voltage (VFB_ > 0.9V), RST becomes high impedance after a 140ms delay and remains high impedance as long as both outputs maintain regulation. Connect a resistor between RST and the logic supply for logic-level voltages.
1
COMP2
2
FB2
3
ILIM2
4
OSC
5 6 7 8
V+ REF GND CKO
9
SYNC
10
ILIM1
11
FB1
12
COMP1
13
RST
6
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR
Pin Description (continued)
PIN 14 15 16 17 18 19 20 21 22 23 24 NAME DH1 LX1 BST1 DL1 PGND VL DL2 BST2 LX2 DH2 EN FUNCTION High-Side Gate Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1. External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver. Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic capacitor and diode according to Figure 1. Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to VL. Power Ground Internal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers and external boost circuitry for the high-side gate drivers. Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to VL. Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic capacitor and diode according to Figure 1. External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver. High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2. Active-High Enable Input. A logic low shuts down both controllers. Connect to VL for always-on operation.
MAX1875/MAX1876
Detailed Description
DC-DC PWM Controller
The MAX1875/MAX1876 step-down converters use a PWM voltage-mode control scheme (Figure 2) for each out-of-phase controller. The controller generates the clock signal by dividing down the internal oscillator or SYNC input when driven by an external clock, so each controller's switching frequency equals half the oscillator frequency (fSW = fOSC/2). An internal transconductance error amplifier produces an integrated error voltage at the COMP pin, providing high DC accuracy. The voltage at COMP sets the duty cycle using a PWM comparator and a ramp generator. At each rising edge of the clock, REG1's high-side N-channel MOSFET turns on and remains on until either the appropriate duty cycle or until the maximum duty cycle is reached. REG2 operates outof-phase, so the second high-side MOSFET turns on at each falling edge of the clock. During each high-side MOSFET's on-time, the associated inductor current ramps up. During the second-half of the switching cycle, the highside MOSFET turns off and the low-side N-channel MOSFET turns on. Now the inductor releases the stored energy as its current ramps down, providing current to the output. Under overload conditions, when the induc-
tor current exceeds the selected valley current-limit (see the Current-Limit Circuit (ILIM_) section), the high-side MOSFET does not turn on at the appropriate clock edge and the low-side MOSFET remains on to let the inductor current ramp down.
Synchronized Out-of-Phase Operation
The two independent regulators in the MAX1875/ MAX1876 operate 180 out-of-phase to reduce input filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component cost and saves board space, making the MAX1875/MAX1876 ideal for cost-sensitive applications. Dual-switching regulators typically operate both controllers in-phase, and turn on both high-side MOSFETs at the same time. The input capacitor must then support the instantaneous current requirements of both controllers simultaneously, resulting in increased ripple voltage and current when compared to a single switching regulator. The higher RMS ripple current lowers efficiency due to power loss associated with the input capacitor's effective series resistance (ESR). This typically requires more low-ESR input capacitors in parallel to minimize input voltage ripple and ESR-related losses, or to meet the necessary ripple-current rating.
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
VIN 6V - 23V RV+ 4.7
0.1F
V+ CV+ 0.22F CIN1 2 x 10F 4.7 BST1 CBST1 0.1F OUTPUT1 VOUT = 1.8V COUT1 4 x 220F L1 1H NH1* DH1 LX1 R1A 8.06k ** NL1* DL1 PGND
VL 4.7 BST2 CBST2 0.1F DH2 LX2 DL2 NL2* ** R2A 15k COUT2 4 x 220F NH2* CVL 4.7F CIN2 2 x 10F
L2 1.2H
OUTPUT2 VOUT = 2.5V
FB1 R1B 10k CCOMP1A 10nF D2 CMSSH-3 OSC RCOMP1 5.9k COMP1 CCOMP1B 100pF MAX1875 MAX1876
FB2 RCOMP2 8.2k COMP2 CCOMP2B 100pF REF GND D3 CMSSH-3 CREF 0.22F CCOMP2A 6.8nF R2B 10k
CLOCK OUTPUT RESET OUTPUT ON
CKO SYNC RST (MAX 1876 ONLY) ILIM1 140k EN ILIM2 96.5k VL 118k
OFF 84.5k
*IRF7811W **OPTIONAL
Figure 1. Standard Application Circuit
With dual synchronized out-of-phase operation, the MAX1875/MAX1876's high-side MOSFETs turn-on 180 out-of-phase. The instantaneous input current peaks of both regulators no longer overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the required input capacitor ripple-current rating, allowing fewer or less expensive capacitors, and reduces shielding requirements for EMI. The Out-of-Phase Waveforms in the Typical Operating Characteristics demonstrate synchronized 180 out-of-phase operation.
Internal 5V Linear Regulator (VL)
All MAX1875/MAX1876 functions are internally powered from an on-chip, low-dropout 5V regulator. The maximum regulator input voltage (V+) is 23V. Bypass the regulator's output (VL) with a 4.7F ceramic capacitor to PGND. The VL dropout voltage is typically 500mV, so when V+ is greater than 5.5V, VL is typically 5V. The MAX1875/MAX1876 also employs an undervoltage lockout circuit that disables both regulators when V L falls below 4.5V. VL should also be bypassed to GND with a 0.1F capacitor.
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
REF VREF 2.0V GND COMP1 BST1 FB1 CONVERTER #1 DH1 SOFT-START DAC LX1 R S Q Q DL1 PGND OSC SYNC CK0 5A RST (MAX1876 ONLY) RESET ILIM1 5V LINEAR REGULATOR V+
MAX1875 MAX1876
VL
OSCILLATOR
EN VREF VL BST2 DH2 LX2 DL2 ILIM2 UVLO AND SHUTDOWN VL - 0.5V
CONVERTER 2 COMP2 FB2
Figure 2. Functional Diagram
The internal VL linear regulator can source over 50mA to supply the IC, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. When driving large FETs, little or no regulator current may be available for external loads.
For example, when switched at 600kHz, a single large FET with 18nC total gate charge requires 18nC 600kHz = 11mA. To drive larger MOSFETs, or deliver larger loads, connect VL to an external power supply from 4.75V to 5.5V.
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
High-Side Gate-Drive Supply (BST_) Gate-drive voltages for the high-side N-channel switches are generated by the flying-capacitor boost circuits (Figure 3). A boost capacitor (connected from BST_ to LX_) provides power to the high-side MOSFET driver. On startup, the synchronous rectifier (low-side MOSFET) forces LX_ to ground and charges the boost capacitor to 5V. On the second half-cycle, after the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BST_ and DH_. This provides the necessary gate-to-source voltage to turn on the highside switch, an action that boosts the 5V gate-drive signal above VIN. The current required to drive the highside MOSFET gates (fSWITCH QG) is ultimately drawn from VL. MOSFET Gate Drivers (DH_, DL_) The DH and DL drivers are optimized for driving moderate-size N-channel high-side and larger low-side power MOSFETs. This is consistent with the low-duty factor seen with large VIN - VOUT differential. The DL_ low-side drive waveform is always the complement of the DH_ high-side drive waveform (with controlled dead time to prevent cross-conduction or "shoot-through"). An adaptive dead-time circuit monitors the DL_ output and prevents the high-side FET from turning on until DL_ is fully off. There must be a low-resistance, low-inductance path from the DL_ driver to the MOSFET gate in order for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX1875/MAX1876 interprets the MOSFET gate as "off" while there is actually charge still left on the gate. Use very short, wide traces (50mils to 100mils wide if the MOSFET is 1in from the device). The dead time at the DH-off edge is determined by a fixed 30ns internal delay. Synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side Schottky catch diode with a low-resistance MOSFET switch. Additionally, the MAX1875/MAX1876 uses the synchronous rectifier to ensure proper startup of the boost gatedriver circuit and to provide the current-limit signal. The internal pulldown transistor that drives DL_ low is robust, with a 0.5 (typ) on-resistance. This low onresistance helps prevent DL_ from being pulled up during the fast rise-time of the LX_ node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET. However, for high-current applications, some combinations of high- and low-side FETs can cause excessive gate-drain coupling, leading to poor efficiency, EMI, and shoot-through currents. This can be remedied by adding a resistor (typically less than 5) in series with BST_, which increases the turn-on time of the high-side FET without degrading the turn-off time (Figure 3).
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Current-Limit Circuit (ILIM_)
The current-limit circuit employs a "valley" current-sensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element. If the currentsense signal is above the current-limit threshold, the MAX1875/MAX1876 does not initiate a new cycle (Figure 4). Since valley current sensing is employed, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the low-side MOSFET's on-resistance, current-limit threshold, inductor value, and input voltage. The reward for this uncertainty is robust, lossless overcurrent sensing that does not require costly sense resistors. The adjustable current limit accommodates MOSFETs with a wide range of on-resistance characteristics (see the Design Procedure section). The current-limit threshold is adjusted with an external resistor at ILIM_ (Figure 1). The adjustment range is from 50mV to 300mV, corresponding to resistor values of 100k to 600k. In adjustable mode, the current-limit threshold across the low-side MOSFET is precisely 1/10th the voltage seen at ILIM_. However, the current-limit threshold defaults to 100mV when ILIM is tied to VL. The logic threshold for switchover to this 100mV default value is approximately VL - 0.5V. Adjustable foldback current limit reduces power dissipation during short-circuit conditions (see the Design Procedure section). Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by LX_ and PGND. The IC must be mounted close to the low-side MOSFET with short, direct traces making a Kelvin sense connection so that trace resistance does not add to the intended sense resistance of the low-side MOSFET.
Undervoltage Lockout and Startup
If VL drops below 4.5V, the MAX1875/MAX1876 assumes that the supply and reference voltages are too low to make valid decisions and activates the undervoltage lockout (UVLO) circuitry which forces DL and DH low to inhibit switching. RST is also forced low during UVLO. After VL rises above 4.5V, the controller powers up the outputs. Enable (EN), Soft-Start, and Soft-Stop Pull EN high to enable or low to shutdown both regulators. During shutdown the supply current drops to 1mA (max), LX enters a high-impedance state (DH_ connected to LX_, and DL_ connected to PGND), and COMP_ is discharged to GND through a 17 resistor. VL and REF remain active in shutdown. For "always-on" operation, connect EN to VL.
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR
INPUT (VIN)
VL 5
BST_
DH_
LX_
MAX1875
Figure 3. Reducing the Switching-Node Rise Time
On the rising edge of EN both controllers enter softstart. Soft-start gradually ramps up to the reference voltage seen by the error amplifier in order to control the outputs' rate of rise and reduce input surge currents during startup. The soft-start period is 1024 clock cycles (1024/f SW ), and the internal soft-start DAC ramps up the voltage in 64 steps. The output reaches regulation when soft-start is completed. On the falling edge of EN both controllers simultaneously enter softstop, which reverses the soft-start ramp. The part enters shutdown after soft-stop is complete.
MAX1875/MAX1876 support the following three operating modes: * SYNC = GND: The CKO output frequency equals REG1's switching frequency (fCKO = fDH1) and the CKO signal is in phase with REG1's switching frequency. This provides 2-phase operation when synchronized with a second slave controller. * SYNC = VL: The CKO output frequency equals two times REG1's switching frequency (fCKO = 2fDH1) and the CKO signal is phase shifted by 90 with respect to REG1's switching frequency. This provides 4-phase operation when synchronized with a second MAX1875/MAX1876 (slave controller). * SYNC Driven by External Oscillator: The controller generates the clock signal by dividing down the SYNC input signal, so that the switching frequency equals half the synchronization frequency (f SW = fSYNC/2). REG1's conversion cycles initiate on the rising edge of the internal clock signal. The CKO output frequency and phase match REG1's switching frequency (f CKO = f DH1 ) and the CKO signal is in phase. Note that the MAX1875/MAX1876 still require ROSC when SYNC is externally clocked and the internal oscillator frequency should be set to 50% of the synchronization frequency (fOSC = 0.5 fSYNC).
MAX1875/MAX1876
Thermal Overload Protection
Thermal overload protection limits total power dissipation in the MAX1875/MAX1876. When the device's die-junction temperature exceeds TJ = +160C, an on-chip thermal sensor shuts down the device, forcing DL_ and DH_ low, allowing the IC to cool. The thermal sensor turns the part on again after the junction temperature cools by 10C. During thermal shutdown, the regulators shut down, RST goes low, and soft-start is reset. If the VL linear-regulator output is short-circuited, thermal-overload protection is triggered.
Reset Output (MAX1876 Only)
RST is an open-drain output. RST pulls low when either output falls below 90% of its nominal regulation voltage. Once both outputs exceed 90% of their nominal regulation voltages and both soft-start cycles are completed, RST goes high impedance. To obtain a logic-voltage output, connect a pullup resistor from RST to the logic supply voltage. A 100k resistor works well for most applications. If unused, leave RST grounded or unconnected.
Design Procedure
Effective Input Voltage Range
Although, the MAX1875/MAX1876 controllers can operate from input supplies ranging from 4.75V to 23V, the input voltage range can be effectively limited by the MAX1875/MAX1876s' duty-cycle limitations. The maximum input voltage is limited by the minimum on-time (tON(MIN)): VIN(MAX) VOUT t ON(MIN)fSW
Clock Synchronization (SYNC, CKO)
SYNC serves two functions: SYNC selects the clock output (CKO) type used to synchronize slave controllers, or it serves as a clock input so the MAX1875/MAX1876 can be synchronized with an external clock signal. This allows the MAX1875/MAX1876 to funtion as either a master or slave. CKO provides a clock signal synchronized to the MAX1875/MAX1876s' switching frequency, allowing either in-phase (SYNC = GND) or 90 out-of-phase (SYNC = VL) synchronization of additional DC-DC controllers (Figure 5). The
______________________________________________________________________________________
11
Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
-IPEAK
the sum of the resistances in the charging path, including high-side switch, inductor, and PC board resistances.
ILOAD INDUCTOR CURRENT
Setting the Output Voltage
For 1V or greater output voltages, set the MAX1875/ MAX1876 output voltage by connecting a voltagedivider from the output to FB_ to GND (Figure 6). Select R_B (FB_ to GND resistor) to between 1k and 10k. Calculate R_A (OUT_ to FB_ resistor) with the following equation: V R _ A = R _ B OUT -1 VSET where VSET = 1V (see the Electrical Characteristics) and VOUT can range from VSET to 18V. For output voltages below 1V, set the MAX1875/ MAX1876 output voltage by connecting a voltagedivider from the output to FB_ to REF (Figure 6). Select R_C (FB to REF resistor) in the 1k to 10k range. Calculate R_A with the following equation: V V R _ A = R _ C SET- OUT VREF-VSET where V SET = 1V, V REF = 2V (see the Electrical Characteristics), and VOUT can range from 0 to VSET.
ILIMIT
0
TIME
Figure 4. "Valley" Current-Limit Threshold Point
where tON(MIN) is 100ns. The minimum input voltage is limited by the switching frequency and minimum offtime, which determine the maximum duty cycle (DMAX = 1 - fSWtOFF(MIN)): V + VDROP1 VIN(MIN) = OUT + VDROP2 - VDROP1 1- fSW t OFF(MIN) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances. VDROP2 is
MAX1875
OSC CK0 SYNC VL MASTER SYNC OSC
MAX1875
CK0 SYNC VL MASTER SYNC
MAX1875
OSC
SLAVE
SLAVE
2-PHASE SYSTEM 180 PHASE SHIFT DH1 MASTER DH2 DH1 SLAVE DH2 SLAVE DH2 MASTER DH2 DH1 90 PHASE SHIFT DH1
4-PHASE SYSTEM
Figure 5. Synchronized Controllers
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR
Setting the Switching Frequency
The controller generates the clock signal by dividing down the internal oscillator or SYNC input signal when driven by an external oscillator, so the switching frequency equals half the oscillator frequency (fSW = fOSC/2). The internal oscillator frequency is set by a resistor (ROSC) connected from OSC to GND. The relationship between fSW and ROSC is: 6 x 109 - Hz S Switching Frequency section). The exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but also improve transient response and reduce efficiency due to higher peak currents. On the other hand, higher inductance increases efficiency by reducing the RMS current. However, resistive losses due to extra wire turns can exceed the benefit gained from lower AC current levels, especially when the inductance is increased without also allowing larger inductor dimensions. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The inductor's saturation rating must exceed the peakinductor current at the maximum defined load current (ILOAD(MAX)): LIR IPEAK = ILOAD(MAX ) + I 2 LOAD(MAX )
MAX1875/MAX1876
ROSC =
fSW
where fSW is in Hz, fOSC is in Hz, and ROSC is in . For example, a 600kHz switching frequency is set with ROSC = 10k. Higher frequencies allow designs with lower inductor values and less output capacitance. Consequently, peak currents and I2R losses are lower at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase. A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by ROSC. This maintains output regulation even with intermittent SYNC signals. When an external synchronization signal is used, ROSC should set the switching frequency to one half SYNC rate (fSYNC).
Setting the Valley Current Limit
The minimum current-limit threshold must be high enough to support the maximum expected load current with the worst-case low-side MOSFET on-resistance value since the low-side MOSFET's on-resistance is used as the current-sense element. The inductor's valley current occurs at ILOAD(MAX) minus half of the ripple current. The current-sense threshold voltage (V ITH ) should be greater than voltage on the low-side MOSFET during the ripple-current valley: LIR VITH > RDS(ONMAX) x ILOAD(MAX) x 1 , 2 where R DS(ON) is the on-resistance of the low-side MOSFET (NL). Use the maximum value for RDS(ON) from the low-side MOSFET's data sheet, and additional margin to account for RDS(ON) rise with temperature is also recommended. A good general rule is to allow 0.5% additional resistance for each C of the MOSFET junction temperature rise. Connect ILIM_ to VL for the default 100mV (typ) current-limit threshold. For an adjustable threshold, connect a resistor (R ILIM _) from ILIM_ to GND. The relationship between the current-limit threshold (VITH_) and RILIM_ is: RILIM _ = VITH _ 0.5A
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX1875/MAX1876: inductance value (L), peak-inductor current (IPEAK), and DC resistance (RDC). The following equation assumes a constant ratio of inductor peak-to-peak AC current to DC average current (LIR). For LIR values too high, the RMS currents are high, and therefore I2R losses are high. Large inductances must be used to achieve very low LIR values. Typically inductance is proportional to resistance (for a given package type) which again makes I2R losses high for very low LIR values. A good compromise between size and loss is a 30% peak-to-peak ripple current to average-current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, and selected LIR determine the inductor value as follows: V (V - V ) L = OUT IN OUT VINfSWIOUTLIR where VIN, VOUT, and IOUT are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by R OSC (see the Setting the
where RILIM_ is in and VITH_ is in V.
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
An RILIM resistance range of 100k to 600k corresponds to a current-limit threshold of 50mV to 300mV. When adjusting the current limit, 1% tolerance resistors minimize error in the current-limit threshold. For foldback current limit, a resistor (RFBI) is added from ILIM pin to output. The value of RILIM and RFBI can then be calculated as follows: First select the percentage of foldback, PFB, from 15% to 30%, then:
MAX1875
OUT_ REF R_C FB_ R_B R_A OUT_
R_A FB_
MAX1875
VOUT_ > 1V VOUT_ < 1V
RFBI = and
PFB x VOUT 5 x 10-6 (1- PFB )
Figure 6. Adjustable Output Voltage
10 x VITH (1- PFB ) x RFBI RILIM = [VOUT -10 x VITH(1- PFB )]
Output Capacitor
The key selection parameters for the output capacitor are capacitance value, ESR, and voltage rating. These parameters affect the overall stability, output ripple voltage, and transient response. The output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor's ESR caused by the current flowing into and out of the capacitor: VRIPPLE VRIPPLE(ESR) + VRIPPLE(C) The output voltage ripple as a consequence of the ESR and output capacitance is: VRIPPLE(ESR) = IP-PRESR VRIPPLE(C) = IP-P 8COUT fSW
Input Capacitor
The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents as defined by the following equation: IRMS = ILOAD VOUT (VIN - VOUT ) VIN
I RMS has a maximum value when the input voltage equals twice the output voltage (VIN = 2V OUT ), so I RMS(MAX) = I LOAD / 2. For most applications, nontantalum capacitors (ceramic, aluminum, polymer, or OS-CON) are preferred at the input due to their robustness with high inrush currents typical of systems that can be powered from very low impedance sources. Additionally, two (or more) smaller-value low-ESR capacitors can be connected in parallel for lower cost. Choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal long-term reliability.
V -V V IP-P = IN OUT OUT fSWL VIN where IP-P is the peak-to-peak inductor current (see the Inductor Selection section). These equations are suitable for initial capacitor selection, but final values should be verified by testing in a prototype or evaluation circuit.
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR
As a general rule, a smaller inductor ripple current results in less output ripple voltage. Since inductor ripple current depends on the inductor value and input voltage, the output ripple voltage decreases with larger inductance and increases with higher input voltages. However, the inductor ripple current also impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output-voltage sag is also a function of the maximum duty factor, which can be calculated from the minimum off-time and switching frequency: V L(ILOAD1 - ILOAD2 )2 OUT + t OFF(MIN) VINfSW VSAG = VIN - VOUT 2COUT VOUT - t OFF(MIN) VINfSW where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics), and fSW is set by ROSC (see the Setting the Switching Frequency section). assuming an ideal integrator, and assuming that CCOMP_B is much less than CCOMP_A. ALX / COMP = VLX VCOMP = VIN VRAMP
MAX1875/MAX1876
for frequencies lower than Nyquist. 1+ sRESRCOUT V V AFB / LX = FB = SET 2 VLX VOUT S LCOUT + SRESRCOUT + 1 1+ SRESRCOUT V SET VOUT VOUT S2LCOUT + 1 Therefore: AL gM _ COMP SCCOMP _ A x 1 + SRCOMPCCOMP _ A 1 + SRCOMPCCOMP _ B
OUT
x
VIN VRAMP
V 1 + SRESR COUT x SET x VOUT S2 LC +1 For an ideal integrator this loop gain approaches infinity at DC. In reality the g M amplifier has a finite output impedance which imposes a finite, but large, loop gain. It is this large loop gain that provides DC load accuracy. The dominant pole occurs due to the integrator, and for this analysis, it can be approximated to occur at DC. RCOMP creates a zero at: fZ _ COMP _ A = 1 2 x RCOMP _ CCOMP _ A
Compensation
Each voltage-mode controller section employs a transconductance error amplifier whose output is the compensation point of the control loop. The control loop is shown in Figure 7. For frequencies much lower than Nyquist, the PWM block can be simplified to a voltage amplifier. Connect RCOMP_ and CCOMP_A from COMP to GND to compensate the loop (see Figure 7). The inductor, output capacitor, compensation resistor, and compensation capacitors determine the loop stability. Since the inductor and output capacitor are chosen based on performance, size, and cost, select the compensation resistor and capacitors to optimize controlloop stability. To determine the loop gain (AL), consider the gain from FB to COMP (ACOMP/FB), from COMP to LX (ALX/COMP), and from LX to FB (AFB/LX). The total loop gain is: AL = A COMP / FB x ALX / COMP x AFB / LX where: gM _ COMP V x ACOMP / FB = COMP VFB SCCOMP 1 + sRCOMPCCOMP _ A 1 + sRCOMPCCOMP _ B
The inductor and capacitor form a double pole at: fLC = 1 2 x LCOUT
At some higher frequency the output capacitor's impedance becomes insignificant compared to its ESR, and the LC system becomes more like an LR system, turning a double pole into a single pole. This zero occurs at: fESR = 1 2 x RESR COUT
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15
Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
P W VC M DL LX N RESR DH GAIN = +VIN/VRAMP FOR FREQUENCIES LOWER THAN NYQUIST N L VOUT L LX
FB COMP_ RCOMP_ gM_GROUP VSET
=
COMP_ gM_GROUP RCOMP_ CCOMP_A CCOMP_B
RESR
COUT
FB
COUT
VSET
CCOMP_A
CCOMP_B
Figure 7. Fixed-Frequency Voltage-Mode Control Loop
A final pole is added using C COMP_B to reduce the gain and attenuate noise after crossover. This pole (fCOMP_B) occurs at: fCOMP _ B = 1 2 x RCOMPCCOMP _ B
fCO = GBW =
V x SET VRAMP VOUT gM _ COMP x RCOMP x RESR x 2 x L
VIN
Figure 8 shows a Bode plot of the poles and zeros in their relative locations. Near crossover the following approximations can be made to simplify the loop-gain equation: * RCOMP has much higher impedance than CCOMP. This is true if, and only if, crossover occurs above fZ_COMP_A. If this is true, CCOMP_A can be ignored (as a short to ground). * RESR is much higher impedance than COUT. This is true if, and only if, crossover occurs well after the output capacitor's ESR zero. If this is true, C OUT becomes an insignificant part of the loop gain and can be ignored (as a short to ground). * CCOMP_B is much higher impedance than RCOMP and can be ignored (as an open circuit). This is true if, and only if, crossover occurs far below fCOMP_B. The following loop gain equation can be found by using these previous approximations with Figure 7: AL VIN V x SET x VRAMP VOUT gM _ COMP x RCOMP x RESR sL
To ensure stability, select RCOMP to meet the following criteria: * Unity-gain crossover must occur below 1/5th of the switching frequency. * For reasonable phase margin using type 1 compensation, fCO must be larger than 5 fESR. Choose CCOMP_A so that fZ_COMP_A equals half fLC using the following equation: CCOMP _ A = 2 x LCOUT RCOMP
Choose CCOMP_B so that fCOMP_B occur at 3 times fCO using the following equation: CCOMP _ B =
2 x 3 x fCO x RCOMP
(
1
)
MOSFET Selection
The MAX1875/MAX1876s' step-down controller drives two external logic-level N-channel MOSFETs as the circuit switch elements. The key selection parameters are: * On-resistance (RDS(ON)) * Maximum drain-to-source voltage (VDS(MAX))
Setting the loop gain to 1 and solving for the crossover frequency yields:
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR
BODE PLOT FOR VOLTAGEMODE CONTROLLERS
50 40 30 20 GAIN (dB) 10 0 -10 -20 -30 -40 0.001 0.01 0.1 1 fCOMP_B fZ-COMP_A fESR fCO fSWITCH fLC
NL _ according to duty factor as shown in the equations below. Switching losses affect only the high-side MOSFET, since the low-side MOSFET is a zero-voltage switched device when used in the buck topology. Calculate MOSFET temperature rise according to package thermal-resistance specifications to ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature. The worst-case dissipation for the high-side MOSFET (PNH) occurs at both extremes of input voltage, and the worst-case dissipation for the low-side MOSFET (PNL) occurs at maximum input voltage. Q VI f + QGD PNH(SWITCHING) = IN LOAD OSC GS 2 IGATE IGATE is the average DH driver output current capability determined by: IGATE = 2 RDS(ON)DH + RGATE
MAX1875/MAX1876
FREQUENCY (MHz)
Figure 8. Voltage-Mode Loop Analysis
* Minimum threshold voltage (VTH(MIN)) * Total gate charge (Qg) * Reverse transfer capacitance (CRSS) * Power dissipation All four N-channel MOSFETs must be a logic-level type with guaranteed on-resistance specifications at VGS 4.5V. For maximum efficiency, choose a high-side MOSFET (NH_) that has conduction losses equal to the switching losses at the optimum input voltage. Check to ensure that the conduction losses at minimum input voltage do not exceed MOSFET package thermal limits, or violate the overall thermal budget. Also, check to ensure that the conduction losses plus switching losses at the maximum input voltage do not exceed package ratings or violate the overall thermal budget. Ensure that the MAX1875/MAX1876 DL_ gate drivers can drive N L _. In particular, check that the dv/dt caused by NH _ turning on does not pull up the NL _ gate through NL _'s drain-to-gate capacitance. This is the most frequent cause of cross-conduction problems. Gate-charge losses are dissipated by the driver and do not heat the MOSFET. All MOSFETs must be selected so that their total gate charge is low enough that VL can power all four drivers without overheating the IC: PVL = VIN x QG _ TOTAL x fSW MOSFET package power dissipation often becomes a dominant design factor. I2R power losses are the greatest heat contributor for both high-side and low-side MOSFETs. I2R losses are distributed between NH_ and
(
VL
)
where RDS(ON)DH is the high-side MOSFET driver's onresistance (5 max), and RGATE is any series resistance between DH and BST (Figure 3). V PNH(CONDUCTION) = ILOAD2RDS(ON)NH OUT VIN PNH(TOTAL) = PNH(SWITCHING) + PNH(CONDUCTION) V PNL = ILOAD2RDS(ON)NL 1- OUT VIN where PNH(CONDUCTION) is the conduction power loss in the high-side MOSFET, and PNL is the total low-side power loss. To reduce EMI caused by switching noise, add a 0.1F ceramic capacitor from the high-side switch drain to the low-side switch source or add resistors in series with DL_ and DH_ to increase the MOSFETs' turn-on and turn-off times.
Applications Information
Dropout Performance
When working with low input voltages, the output-voltage adjustable range for continuous-conduction operation is restricted by the minimum off-time (tOFF(MIN)). For best dropout performance, use the lowest (100kHz) switching-frequency setting. Manufacturing tolerances and internal propagation delays introduce an error to
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
the switching frequency and minimum off-time specifications. This error is more significant at higher frequencies. Also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the maximum on-time (IUP). The ratio h = IUP/IDOWN is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V SAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows tradeoffs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: V + VDROP1 VIN(MIN) = OUT + VDROP2 - VDROP1 1- hfSW t OFF(MIN) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path, including high-side switch, inductor, and PC board resistances; and t OFF(MIN) is from the Electrical Characteristics. The absolute minimum input voltage is calculated with h = 1. If the calculated V+(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate V SAG to be sure of adequate transient response. Dropout Design Example: VOUT = 5V fSW = 600kHz tOFF(MIN) = 250ns VDROP1 = VDROP2 = 100mV h = 1.5 5V + 100mV VIN(MIN) = 1- 1.5(600kHz)(250ns) +100mV - 100mV = 6.58V Calculating again with h = 1 gives the absolute limit of dropout: 5V + 100mV VIN(MIN) = 1- (600kHz)(250ns) +100mV - 100mV = 6V Therefore, VIN must be greater than 6V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 6.58V.
Improving Noise Immunity
Applications where the MAX1875/MAX1876 must operate in noisy environments can typically adjust their controller's compensation to improve the system's noise immunity. In particular, high-frequency noise coupled into the feedback loop causes jittery duty cycles. One solution is to lower the crossover frequency (see the Compensation section).
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. This is especially true for dual converters where one channel can affect the other. Refer to the MAX1875/MAX1876 EV kit data sheet for a specific layout example. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: * Isolate the power components on the top side from the analog components on the bottom side with a ground shield. Use a separate PGND plane under the OUT1 and OUT2 sides (referred to as PGND1 and PGND2). Avoid the introduction of AC currents into the PGND1 and PGND2 ground planes. Run the power plane ground currents on the top side only. * Use a star ground connection on the power plane to minimize the crosstalk between OUT1 and OUT2. * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Connect GND and PGND together close to the IC. Do not connect them together anywhere else. Carefully follow the grounding instructions under step 4 of the Layout Procedure section.
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR
* Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper PC boards (2oz vs. 1oz) to enhance full-load efficiency by 1% or more. * LX_ and PGND connections to the synchronous rectifiers for current limiting must be made using Kelvin sense connections to guarantee the current-limit accuracy. With 8-pin SO MOSFETs, this is best done by routing power to the MOSFETs from outside using the top copper layer, while connecting PGND and LX_ underneath the 8-pin SO package. * When trade-offs in trace lengths must be made, allow the inductor-charging path to be made longer than the discharge path. Since the average input current is lower than the average output current in step-down converters, this minimizes the power dissipation and voltage drops caused by board resistance. For example, allow some extra distance between the input capacitors and the high-side MOSFET rather than to allow distance between the inductor and the low-side MOSFET or between the inductor and the output filter capacitor. * Ensure that the feedback connection to C OUT_ is short and direct. * Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from the sensitive analog areas (REF, COMP_, ILIM_, and FB_). Use PGND1 and PGND2 as EMI shields to keep radiated noise away from the IC, feedback dividers, and analog bypass capacitors. * Make all pin-strap control input connections (ILIM_, SYNC, and EN) to analog ground (GND) rather than power ground (PGND).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (NL _ source, CIN_, and COUT_). Make all these connections on the top layer with wide, copper-filled areas (2oz copper recommended). 2) Mount the controller IC adjacent to the synchronous rectifier MOSFETs (NL _), preferably on the back side in order to keep LX_, PGND_, and DL_ traces short and wide. The DL_ gate trace must be short and wide, measuring 50mils to 100mils wide if the low-side MOSFET is 1in from the controller IC. 3) Group the gate-drive components (BST_ diodes and capacitors, and VL bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as follows: create a small analog ground plane near the IC. Connect this plane to GND and use this plane for the ground connection for the reference (REF) V+ bypass capacitor, compensation components, feedback dividers, OSC resistor, and ILIM_ resistors (if any). Connect GND and PGND together under the IC (this is the only connection between GND and PGND). 5) On the board's top side (power planes), make a star ground to minimize crosstalk between the two sides.
MAX1875/MAX1876
Chip Information
TRANSISTOR COUNT: 6688 PROCESS: BiCMOS
______________________________________________________________________________________
19
Dual 180 Out-of-Phase PWM StepDown Controllers with POR MAX1875/MAX1876
Typical Operating Circuit
VIN 4.75V TO 23V
V+
VL
BST1
BST2
DH1 OUTPUT1 = 1.8V, 10A LX1 NL1 DL1 PGND
DH2 LX2 DL2
NH2 OUTPUT2 = 2.5V, 10A
NL2
FB1
FB2
COMP1
COMP2
MAX1876 REF OSC GND CLOCK OUTPUT RESET OUTPUT ON EN OFF ILIM2 CK0 SYNC RST ILIM1 VL
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Dual 180 Out-of-Phase PWM StepDown Controllers with POR
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX1875/MAX1876
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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